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Senior Design Manager
Category: Computing, Publishing
  • Your pay will be discussed at your interview

Job code: lhw-e0-78928957

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  Job posted:   Wed Oct 18, 2017
  Distance to work:   ? miles
  3 Views, 0 Applications  
Senior Design Manager

# Senior Design Manager

Job Number: 113154644

Santa Clara Valley, California, United States

Posted: 16-Oct-2017

Weekly Hours: 40.00

**Job Summary**

In this highly visible role, you will be at the center of a SOC/chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will interface with architects.

**Key Qualifications**

* The ideal candidate will have a Masters degree in EE with 10+ years of work experience.

* RTL Logic Design experience of multi-million gate ASICs

* Hands on experience for all aspects of the chip development process with proficiency in Front end tools and methodologies

* Experience with micro-architecture of chip-level interconnect, clocking and power management.

* Experience with timing closure on high speed, low power designs Experience in synthesis flows, DFT and power synthesis, physical synthesis Experience in low power design and implementation technique, knowledge of UPF and power intent verification a plus.

* Knowledge in bring up and lab debug of FPGAs and silicon


As a Senior Design Manager, you will have responsibilities spanning all aspects of SoC design and chip bring up:

Work with your design team on getting a high quality design completed on time oWork with Architecture on microarchitecture and feasibility studies

Work with Verification team to debug functionality of complicated SoC oWork with other IP providers to integrate them into the SoC

Work with CAD on methodology from RTL to gates, including DFT flows oInterface to PD on all FE release deliverable and associated feedback oWork with verification/validation on emulation platforms


BS in Computer Engineering, Electrical Engineering, or Computer Science is required. MS or Ph.D., highly desired

**Additional Requirements**

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