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Performance Model Development and Analysis
Category: Computing, Publishing
  • Your pay will be discussed at your interview

Job code: lhw-e0-78928954

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  Job posted:   Wed Oct 18, 2017
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Performance Model Development and Analysis

# Performance Model Development and Analysis

Job Number: 113154542

Santa Clara Valley, California, United States

Posted: 16-Oct-2017

Weekly Hours: 40.00

**Job Summary**

In this highly visible role, you will be a member of an performance model development effort interfacing with many disciplines, with a critical impact on future architectural performance, power, and area improvements.

**Key Qualifications**

* Strong problem solving and analytical skills

* Strong SW skills with good understanding of modular object oriented software development

* Knowledge of C/C++, Python, Lua, Perl preferred

* Model development and analysis experience preferred

* Outstanding written and verbal communications

* Excellent collaboration skills

* Proficiency in computer/SoC architecture and performance trade-offs

* Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging tools

* Ability to conduct experiments in all phases of design, gathering and analyzing data; and utilize scripting/spread sheet to document and present the results.**Description**

As a performance model developer for the IP blocks you will have responsibilities spanning all aspects of SOC performance, power, and area trade offs:

Working with architecture and design teams to plan and implement a high level performance model. The performance model is minimal feature set to meet the model requirements yet modular and flexible enough to be adapted for new projects and experiments.

Planning and analyzing results of performance studies for different micro-architectural proposals

Providing feedback to the architecture and design teams regarding the micro-architectural choices that may have been made.

Correlating performance model against the performance specifications, expectations, and help the verification team correlate against the RTL implementation.


BS/MS in EE/CS is required

**Additional Requirements**

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