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DRAM Packaging Engineer
Category: Computing, Publishing
  • Your pay will be discussed at your interview

Job code: lhw-e0-84952485

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  Job posted:   Fri Feb 23, 2018
  Distance to work:   ? miles
  2 Views, 0 Applications  
DRAM Packaging Engineer

# DRAM Packaging Engineer

Job Number: 113525822

Santa Clara Valley, California, United States

Posted: 21-Feb-2018

Weekly Hours: 40.00

**Job Summary**

10+ years of experience in Semiconductor Packaging Design, Process and Material development

Excellent engineering problem solving skills, with strong engineering physics

Expert in basic package assembly process: wire bonding / molding / die saw / die stacking

Strong experience in advanced packaging technology - TSV / Flip-chip / Wafer-Level

Knowledge in memory device architecture / physics, design, and test is a plus

Strong program management / execution skill.

**Key Qualifications**

* Lead Memory package development

* Responsible for troubleshooting and root-causing packaging excursions from development to high volume production

* Create, execute, and analyze Design of Experiments (DOE) for packaging development and sustaining activities

* Direct interface with vendors for high density / high bandwidth memory package development, and qualification

* Lead advanced memory interconnection development - Flip-chip / TSV

* Drive industry with advanced package process, new material, and leading edge specs

* 10% Traveling


o MS Degree or PhD in Mechanical / Materials Engineering


**Additional Requirements**

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